I. Field of the Disclosure
The technology of the disclosure relates generally to accessing memory in a processor-based system, and more particularly to decoding systems provided in a memory system for decoding an address in a memory access operation to access a memory row in a memory associated with the address.
II. Background
Processor-based systems include one or more central processing units (CPUs) or other processors that utilize memory for data storage for varying types of system operations and purposes. For example, system memory is provided for data storage and to store program code for storing instructions to be executed. Cache memory may be provided as fast random access memory (RAM) for storing a portion of main memory to avoid longer latency accesses to system memory. Memory buffers are also commonly employed in a processor-based system for storing and controlling the flow of data. For example, a memory buffer may be provided in the form of a first-in, first-out (FIFO) buffer or list. As an example, a FIFO buffer may be employed in instruction pipelines in processors for storing processed instructions in various stages towards execution.
In this regard, a conventional memory system includes a memory array that comprises a plurality of memory rows. Each memory row includes a plurality of bit cells for storing data. To index a memory row in the memory array for a memory access operation (e.g., a memory read or write operation), an encoded address is provided as part of the memory access request. The encoded address is decoded by a decode circuit. The decode circuit outputs a pre-decoded address onto a plurality of decode wordlines such that one of the decode wordlines is activated as a single “hot bit.” Each memory row includes a logic circuit(s) that taps off of the decode wordlines such that a memory row is activated based on the decode wordlines containing the desired hot bit to activate the memory row.
To increase read performance of such a memory system, it may be desired to configure the memory system to automatically read adjacent addresses (i.e., memory rows) in the memory array for applications where it is likely that subsequent read operations will be directed to sequential addresses. In this regard, when a requested encoded address for a read operation is provided to activate a memory row at the encoded address, the memory system can be configured to automatically activate a sequential memory row to be read from the memory array simultaneously as part of a single read operation. However, the addresses in the memory array may not be physically organized in a sequential manner. For example, sequential logical addresses may correspond to interleaved or otherwise separated memory rows in the memory array. In this regard, the logic circuits for the memory rows can be configured to tap the pre-decode wordlines such that a memory row is activated when a sequential logical address is addressed. However, the logic circuits provided for each memory row to allow a memory row to be activated by more than one logical address cause the memory rows to increase in area.
To address this issue, the decoding of the encoded address can be provided among a plurality of partial decoders. A pre-decoded address is first partially decoded into a single-hot bit provided onto a plurality of pre-decode wordlines. Final row decoder circuits are provided for each respective memory row that tap off the pre-decode wordlines to perform the final decoding of the pre-decoded address for activating its respective memory row. However, multiple final row decoder circuits have to be provided for each memory row and be tapped of the pre-decode wordlines if each memory row can be activated by more than one logical address. This increases wiring and routing complexity for the memory rows. Further, providing additional final row decoder circuits for each memory row that are tapped on the pre-decode wordlines increases gate capacitance and memory row access latency as a result.